The present invention relates to testing integrated circuit designs using automatic test pattern generation (ATPG). More particularly, the present invention relates to implementation of an assertion check in a scan cell used in ATPG to ensure that necessary conditions for performing an ATPG procedure are satisfied.
An important step in the development and design of an integrated circuit is testing to detect faults in the circuit design. Testing of an integrated circuit generally involves adding partial or full scan to a circuit design using an ATPG program. The ATPG program generates a set of test patterns to identify faults in the integrated circuit design, which are applied to the input pins of the integrated circuit under test. The response of the integrated circuit to the test patterns is examined at the output pins of the integrated circuit to detect logic faults in the circuit design. A test pattern generally comprises a sequence of bits in the form of a vector, which is sequentially shifted through the storage elements of the integrated circuit.
FIG. 1 is a flow chart diagramming the steps involved in ATPG for testing an integrated circuit using an ATPG tool, such as FastScan or TetraMAX. A standard ATPG program generally initializes in step 10 by invoking a set of input information describing the integrated circuit under test. Typically, the input information comprises a netlist, such as a Verilog netlist, defining the circuit design and an ATPG library defining primitives and arrays for the circuit design. Verilog is a Hardware Description Language (HDL) for electronic design and gate level simulation and the netlist comprises a test file description of a physical connection of components in the circuit design. The ATPG program then switches to a setup mode and invokes a setup file containing list of commands in step 11. Next, in step 12, the ATPG program performs a scan extraction. Scan extraction involves reading the description of the circuit under test and calculating testability measurements for the circuit using design rules checking (DRC). The ATPG program identifies and debugs any design errors in the circuit in step 13.
The ATPG program then proceeds to fault simulation and test pattern generation. Test pattern generation may be random, sequential, or fast sequence test pattern generation. Fault simulation is used to simulate the circuit design on a computer to facilitate the identification of defects in the actual circuit. During fault simulation, possible defects are inserted into the simulated circuit design to simulate and anticipate the response of the circuit to these defects. In step 14, the ATPG program compiles a list of potential faults for the circuit and generates test patterns that simulate each fault in the list in step 15. The test generation algorithm creates test patterns that simulate each of the potential fault types for the circuit under test. In step 16, the test patterns are saved in various pattern formats. Generally, the test patterns are saved in Verilog, VHDL, EDIF or any suitable format. In step 17, a fault coverage report is generated, which describes the percentage of potential faults from the fault list that are successfully simulated.
In step 18, the test patterns are applied to a circuit under test and the output response is analyzed to identify faults in the circuit design. The circuit under test is switched to a test mode and the patterns generated by the ATPG tool are shifted through a scan portion of the circuit and output to an output pin. The scan portion comprises a set of storage elements, which form a shift register in test mode. During playback, the output test patterns shifted output the circuit and the vectors generated during fault simulation are compared by an output analyzer. The output analyzer compares the expected response of the circuit to the actual response of the circuit to diagnose and isolate faults that cause failures in the circuit. In step 19, the results are printed to a file and a report identifying the faults detected in the circuit is generated.
xe2x80x9cScan designxe2x80x9d refers to an electronic circuit design technique that facilitates testing of the circuit by making the storage elements of the circuit, which temporarily store logical states within the integrated circuit, scannable. Scan design involves incorporating scan registers into the circuit to form a scan path, thereby increasing the controllability and observability of the circuit. As discussed, the integrated circuit is tested by shifting a test vector generated by an ATPG program through the storage elements to ensure that the integrated circuit is functioning properly. Using scan design, the state of certain points in the circuit may be modified at any time by suspending normal operation and switching to a xe2x80x9ctestxe2x80x9d mode. In standard operation, the shift registers perform normal operational tasks. The storage elements in the shift registers can be switched into a xe2x80x9ctestxe2x80x9d mode and form a scan portion of the integrated circuit. During test mode, test pattern data can be clocked serially through all the scan registers and out of an output pin at the same time as new test pattern data is clocked in from an input pin.
Level Sensitive Scan Design (LSSD), developed by IBM, is a common type of scan design used with ATPG to test a circuit. LSSD uses separate system and scan clocks to distinguish between a standard operating mode and a test mode. In LSSD, level-sensitive latches used on-chip for state information are replaced by master-slave latch pairs, which are tied together into one long shift register. In standard operating mode, each storage-element is a level sensitive latch controlled by a system clock. For test operation, the latches form master/slave pairs, each pair having one scan input, one scan output and two non-overlapping scan clocks, which are held low during system operation but cause the scan data to be latched when pulsed high during scan. New state information is shifted in serially, allowing the core circuitry in the circuit to process this information, and shift out the modified state information to an output pin.
Current ATPG tools, such as those in the xe2x80x9cFastScanxe2x80x9d suite developed by Mentor Graphics and the xe2x80x9cTetraMAXxe2x80x9d suite developed by Synopsys, are used to analyze and classify probable defect sights using a simulation-based approach and a dynamic algorithm. However, many of the currently available ATPG tools used with LSSD cause significant fault coverage loss and test coverage loss and have a negative impact on the performance of the circuit. In other words, many potential design defects cannot be simulated and tested using these tools and of the design defects that can be simulated and tested for, many often go undetected.
In addition, prior scan cells used in ATPG lack a system for ensuring that necessary conditions are satisfied during testing. For example, in a circuit incorporating scan design, the scan cell can switch between a standard operating mode and a test mode, but cannot operate in both modes simultaneously. A system clock controls the input of data into the circuit during the standard operating mode and a scan clock controls the shifting of test pattern data through the scan portion of the circuit during test mode. The system clock and the scan clock must be independent and non-overlapping to differentiate between the standard operating mode and the test mode. Simultaneous activation of the system clock and the scan clock interferes with the shifting of test data through the circuit under test and results in significant inaccuracies and discrepancies Thus, it would be desirable to implement an assertion check to ensure that simultaneous activation of a system clock and a scan clock in a scan cell does not occur.
The illustrative embodiment of the present invention provides an assertion check in a design-for-test scan cell to ensure that necessary conditions for certain signals are satisfied. The assertion check includes an error signal generator within the scan cell that generates an error signal when there is a violation of necessary conditions for testing the integrated circuit using APTG. According to the illustrative embodiment, the scan cell comprises a set-reset flip-flop paired with a latch. The flip-flop is used as a master storage element and the latch is used as a slave storage element to form a scan path. The master flip-flop and the slave latch are connected to form a shift register for shifting test data through the circuit under test. According to the illustrative embodiment, a system clock drives the standard operational mode of the storage elements and a shift clock drives the test mode. An enable clock is used to activate the system clock and switch the scan cell between the standard operational mode and the test mode. The assertion check according to the illustrative embodiment ensures that the enable clock and the shift clock are not both high at the same time, which would be a violation of conditions necessary for performing ATPG testing.
According to the illustrative embodiment, the enable clock signal and the shift clock signal are input to a logic gate, such as an AND gate, or a set of logic gates having an output signal that indicates whether both input signals are high. The output of the logic gate or set of logic gates is connected to a set pin and a reset pin of the master flip-flop. If both the enable clock signal and the shift clock signal are high at the same time, the flip-flop generates an error signal.
The illustrative embodiment of the invention ensures that the necessary conditions for performing ATPG testing are satisfied. The assertion check is relatively simple to implement without affecting the performance of the circuit. Moreover, the assertion check provides a reliable means of detecting inconsistencies during testing of a circuit design.
According to one embodiment a method of performing an assertion check in a scan cell is provided. The scan cell comprises a scanning clock corresponding to a test mode, a system clock corresponding to an operating mode and an enable clock for activating the system clock. The method comprises comparing the scanning clock and the enable clock and generating an error signal if both the scanning clock and the enable clock are high simultaneously.
According to another embodiment, a method of implementing an assertion check in a scan cell is provided. The scan cell comprises a flip-flop connected to a latch, a system clock signal, a scan clock signal and an enable clock signal for activating the system clock signal. The method comprises providing a logic gate having inputs and an output and connecting the enable clock signal and the scan clock signal to the inputs of the logic gate.
According to yet another embodiment, an integrated circuit having scan capabilities is provided. The integrated circuit comprises a master storage element comprising a set-reset flip-flop a slave storage element comprising a latch, a system clock input to the flip-flop for controlling the flip-flop during an operating mode, a scanning clock signal input to the flip-flop for controlling the flip-flop during a test mode, an enable clock signal input for activating the system clock signal and a logic gate for generating an indicator signal indicative of simultaneous activation of the scanning clock signal and the enable clock signal. The master storage element and the slave storage element form a shift register for shifting test data through the integrated circuit to detect faults during the test mode.